1. Technical Field
The present invention relates to data processors. More specifically, the present invention relates to identifying processor implementations.
2. Description of Related Art
Processor architecture defines a Central Processing Unit ID (CPUID) or processor version number (PVR) to identify the specific hardware implementation of the architecture. Identifying the hardware implementation allows software developers to find out what the capabilities and performance level of the current machine are, in order to optimize software development. Bit specifications describe the amount of data that a CPU can compute at the same time, known as the register width. For example, if the clock rates are the same (300 MHz, 500 MHz, etc.) and the basic architectures are equal, a 64-bit computer works twice as fast internally as a 32-bit computer.
Current architectures may define an instruction set for 32-bit and 64-bit implementations within a given processor. For example, if a software developer wants to write a portable software which fully utilizes 64-bit subset instructions for the 64-bit implementation of the architecture, the developer may have to account for all existing 64-bit processors. The software developer may also have to make changes to support any new processor implementations when they become available. The developer accomplishes this task by obtaining the list of PVRs for all 64-bit processors, and then checking the PVR of the current processor running the software to see if the PVR is on the list. The software developer only knows the list of announced processors or pre-announced processors. If the processor developer comes up with a new generation chip in the future, the software developer will need an updated list.
The software developer needs to maintain the list of all existing 64-bit processors of the architecture to utilize any 64-bit feature of the 64-bit implementation. If an architecture defines both 32-bit and 64-bit implementations, and a processor is not on the 64-bit list, then it is a 32-bit processor implementation. All implementations of the architecture always support the lowest common set of instruction, in this case, the 32-bit instruction set. Therefore, if a processor is a 64-bit implementation, it must support the 32-bit instructions as the base subset. With only 32-bit or 64-bit width, one 64-bit list is sufficient. If there are four widths (i.e. 32-, 64-, 128-, and 256-bit), then three lists may be needed for the higher bit-width processors (64-, 128-, and 256-bit).
Currently, there is no permanent way to query the implementation of any existing processor. Instead, software developers have to maintain the list of CPUIDs or PVRs and update the code for future processors. Therefore, it would be desirable to have a method and apparatus for architecturally identifying which implementation is being used in a processor.
The present invention provides a method, system and program for architecturally identifying data processor implementations. The invention comprises assigning a plurality of least significant bits in a processor""s identification register to a unique value. This value can be assigned to these bits permanently during manufacture and is used to identify the bit specification for a specific processor implementation. The present invention can be generalized to include any processor architecture that comprises a plurality of instruction subsets for different bit specifications.